Fabricating biCMOS (bipolar CMOS) for high-speed, high-drive applications. 2. MOS Transistor Theory
) Design Rules : Scalable geometric constraints that ensure layouts remain manufacturable even as fabrication nodes shrink.
Many universities provide condensed summaries based on this text, such as those from VEMU Institute of Technology .
Design for Testability (DFT) using scan paths and built-in self-tests.
The text begins with the evolution of integrated circuits. It explores how fabrication processes have advanced to allow for denser, faster, and more power-efficient chips. 2. Basic Electrical Properties of MOS Circuits
While the book heavily features planar NMOS and early CMOS technologies, the abstract architecture principles taught by Pucknell remain intact in modern chip design:
One of the most praised sections of the book is its approach to physical design layouts:
): The minimum voltage required to create a conduction channel.
Be ready to draw the stick diagram and calculate the layout area for complex Boolean expressions (e.g.,