A deep dive into the basic building blocks of digital logic:
As CMOS technology scaled from micrometer to nanometer regimes, Kang’s subsequent editions (including those co-authored with Chulwoo Kim) adapted to address "Deep Sub-Micron" (DSM) effects. This includes critical discussions on:
to illustrate theoretical concepts with real-world circuit behavior. Updated for Modern Tech : Later editions (such as the 4th) specifically address nanometer-scale CMOS technologies
Addressing the challenge of "static" power consumption as threshold voltages drop.
Before designing complex logic gates, an engineer must master the behavior of individual NMOS and PMOS transistors. The book provides an in-depth analysis of:
is a foundational resource in VLSI design. It covers the entire design flow, from semiconductor physics to complex system-level testing. Table of Contents Overview
It addresses critical modern design challenges, including power dissipation, interconnect delays, and design for manufacturability (DFM). 2. Core Topics Covered in the Book
The book arrived during the mass adoption of Complementary Metal-Oxide-Semiconductor (CMOS) technology. While earlier texts still dwelled on NMOS or Bipolar logic, Kang embraced the low-power, high-noise-margin reality of CMOS. The book systematically explains why CMOS dominates the industry—from a 2-input NAND gate to a multi-million gate microprocessor.
The book includes excellent cross-section diagrams showing the fabrication process (p-well, n-well, twin-tub). These diagrams are frequently scanned and uploaded to lecture slides globally.
"CMOS Digital Integrated Circuits" by Sung-Mo Kang is a renowned textbook that provides an in-depth analysis of CMOS (Complementary Metal-Oxide-Semiconductor) digital integrated circuits. The book is a valuable resource for students, researchers, and professionals in the field of electrical engineering, particularly those interested in VLSI (Very Large Scale Integration) design.
In modern sub-nanometer chips, the wires connecting transistors (interconnects) often slow down the circuit more than the transistors themselves. The text addresses resistance, capacitance, and inductance (RCL) delays, teaching engineers how to model wire geometry and implement clock distribution networks safely. 5. Dynamic Power Minimization